1. Field of the Invention
The present invention relates to MOS active pixel solid-state imaging apparatuses including a plurality of photoelectric conversion components.
2. Description of the Related Art
In the past, there have been known pixels in a MOS active pixel solid-state imaging apparatus (or APS) configured as disclosed in Japanese Patent Laid-Open No. 2006-086241 (called Patent Document 1 hereinafter). Patent Document 1 discloses that a floating diffusion region (FD region) has a lower impurity concentration than the impurity concentration in a drain region of a reset transistor in order to reduce the parasitic capacitance at a node to which the floating diffusion of a pixel is connected.
Japanese Patent Laid-Open No. 2006-073733 (called Patent Document 2 hereinafter) discloses sharing an FD, an amplifier transistor and a reset transistor between a plurality of pixels to reduce the number of transistors per pixel in order to address reduction of the dimensions of pixels due to the increase in number of pixels and a lower sensitivity due to the reduction of dimensions of pixels.
Japanese Patent Laid-Open No. 2008-041726 (called Patent Document 3 hereinafter) discloses a configuration of an apparatus including transistors in a pixel and peripheral circuit, wherein an impurity concentration in source and drain regions of each of the transistors in the pixels is lower than those of the peripheral circuit. This configuration may suppress the generation of hot carriers.
Since each of the pixels in an APS has more transistors, it is important to reduce the area occupied by the transistors as much as possible so as to raise the fill factor of the pixel. In addition to a photoelectric conversion component, a pixel may further include components (regions) such as an FD region, an amplifier transistor, a reset transistor, a select transistor, and a well contact region. The well contact region includes a region of the opposite conduction type of those of the FD and source and drain regions of the transistors. The well contact region is a region for supplying reference voltage to a well providing a channel part of transistors in a pixel.
One way to reduce the area to be occupied by the regions excluding a photoelectric conversion component in a pixel may be to dispose the amplifier transistor and the select transistor within the same active region. The present inventor has studied how the components of a pixel are disposed on four sides surrounding a photoelectric conversion component in the configuration.
First, the amplifier transistor and select transistor occupy a neighboring region of a first side of the photoelectric conversion component. This is because the amplifier transistor and select transistor are electrically connected in series and disposed closely for reduction of wiring resistance and the size of the layout. The FD occupies a region in the vicinity of a second side. Since the symmetry of the pixel layout affects on image quality, the components are disposed symmetrically with each other with respect to a neighboring row or column. From this viewpoint, the FD in a neighboring row or column occupies a region in the vicinity of the third side opposed to the second side.
The reset transistor and well contact region are disposed on the remaining fourth side. As a result, the reset transistor may sometimes have a source region or a drain region closely to a well contact region. As described above, the source and drain regions of the transistor are regions having a conduction type which is opposite to that of the well contact region, and thus form PN junctions. The reduction of pixel dimensions reduces the distance between the source and drain regions of the reset transistor and the well contact region. For this reason, the electric field to be applied to the PN junction gets stronger, and a leak current occurs and flows in the opposite direction. Sometimes, light may be emitted therefrom. A photodiode may detect the flow of charges upon light emission, and thus, the pixel having the photodiode is observed as a point defect.
On the other hand, the configuration as disclosed in Patent Document 3 in which source and drain regions of all MOS transistors within a pixel have a lower impurity concentration may be considered to moderate the electric field.
However, a lower impurity concentration in source and drain regions present on a path where current for reading signals flows increases the resistance. The resistance may cause a voltage drop and reduces the dynamic range. Provided on a path where current for reading signals flows are the amplifier transistor and the select transistor.
Having described up to this point by taking the disposition of the components of a pixel as an example, it is not limited to the described example. The situation may occur when one of source and drain regions of the reset transistor is disposed closely to the well contact region.
In view of the situation, the present invention can moderate the electric field between a reset transistor and a well contact caused by reduction of pixel dimensions, without narrowing the dynamic range, when a plurality of photoelectric conversion components share a pixel readout circuit.